1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having transistors, and more particularly to a semiconductor integrated circuit which operates at lower voltage.
2. Description of the Related Art
Recently, the power supply voltages (operation voltages) of semiconductor integrated circuits have been lowering because of finer transistor structures, reduced power consumption, and so forth. On the other hand, threshold voltages of transistors have little dependence on the power supply voltages. Therefore, as the power supply voltage lowers, the threshold voltages of the transistors with respect to the power supply voltages relatively goes high. As a result, transistors have decreased in operating speed, with increased difficulties in obtaining desired characteristics.
The threshold voltage of a transistor varies with a change in the substrate voltage of the transistor. Specifically, the threshold voltage increases with the backward bias of the pn junction between the source and substrate going higher. Higher threshold voltages of transistors lower the drivabilities of the transistors while reducing non-operation leak currents in the transistors.
Japanese Unexamined Patent Application Publication No. Sho 60-10656 and Japanese Unexamined Patent Application Publication No. Hei 6-89574 disclose examples of changing substrate voltages of transistors in a non-operation state (standby state) and an operation state. According to the semiconductor integrated circuits disclosed in these publications, a plurality of substrate voltage generators for generating different substrate voltages are formed on an integrated circuit, and the substrate voltage generators are switched for use in non-operation periods and operation periods. Then, in the non-operation periods, the threshold voltages of transistors are heightened to reduce leak currents. In the operation periods, the threshold voltages of the transistors are lowered, which enhances the drivabilities and the operating speed of the transistors.
Such conventional semiconductor integrated circuits have had a problem, however, that the plurality of substrate voltage generators have to be formed on a chip with an increase in layout area. In particular, when the circuits are composed of CMOSs, the pMOS transistors and the nMOS transistors each require two substrate voltage generators.
Moreover, semiconductor integrated circuits commonly implement a power-on resetting circuit. The power-on resetting circuit is actuated upon the startup of a power supply so that internal circuits are initialized to avoid malfunctions of the semiconductor integrated circuit. This type of power-on resetting circuit utilizes a threshold voltage of a transistor for detecting that the power supply voltage reaches a predetermined value, and generating a power-on resetting signal. If the threshold voltage of the transistor becomes relatively high with respect to the power supply voltage, the power-on resetting signal might not be generated properly. This can preclude normal initialization of the internal circuits and cause the semiconductor integrated circuit to malfunction.
Furthermore, the lowering in transistor operation voltage requires that substrate voltages be hereafter generated with accuracy in steps of e.g. several hundreds of millivolts, not in steps of 1 V as heretofore.
An object of the present invention is to reduce the consumption current of a transistor during standby periods and improve the drivability of the transistor during operation periods without increasing the layout size.
Another object of the present invention is to reduce the consumption current of a transistor during standby periods and improve the drivability of the transistor during operation periods in the cases where the transistor has a relatively high threshold voltage with respect to its power supply voltage.
Still another object of the present invention is to change the threshold voltage of a transistor in accordance with the operating state of the semiconductor integrated circuit, and to modify transistor characteristics.
Another object of the present invention is to accurately generate substrate voltages to be supplied to transistor substrates.
According to one aspect of the present invention, transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between the first power supply voltage and the second power supply voltage. The substrate voltages are changed to lower threshold voltages of the transistors so that the transistors improve in drivability and operating speed. Therefore, neither a booster for generating higher voltages nor a pumping circuit for generating negative voltages is particularly required. This allows a reduction in layout size. Besides, in accordance with the operating state of the semiconductor integrated circuit, the transistor characteristics can be easily changed by changing the threshold voltages of the transistors. The substrate voltages are set at a value between the first power supply voltage and the second power supply voltage depending on a capacitance ratio. Therefore, it is possible to generate substrate voltages with constant values.
According to another aspect of the present invention, the substrate voltages of the transistors are set at a value at the center of the first power supply voltage and the second power supply voltage. A difference between the first power supply voltage and the substrate voltages is equal to a difference between the second power supply voltage and the substrate voltages. Therefore, variations in the threshold voltages of transistors supplied with the first power supply voltage can be set equal to variations in the threshold voltages of transistors supplied with the second power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate voltages of the transistors are set at either the first power supply voltage or the second power supply voltage during a non-operation period (standby period) of the transistors. The threshold voltages of the transistors during the non-operation period become higher than during the operation period. This reduces leak currents in the transistors during the non-operation period.
According to another aspect of the semiconductor integrated circuit in the present invention, the transistors include a pMOS transistor supplied with the first power supply voltage at its source electrode and an nMOS transistor supplied with the second power supply voltage at its source electrode. A substrate voltage of the pMOS transistor and a substrate voltage of the nMOS transistor are set at a value between the first power supply voltage and the second power supply voltage during an operation period of the transistors. The operation speed of the transistors improves by changing the substrate voltages during the operation periods of the pMOS transistor and the nMOS transistor in order to lower threshold voltages of the transistors.
According to another aspect of the semiconductor integrated circuit in the present invention, the pMOS transistor and the nMOS transistor have lower forward biases between the respective sources and substrates during the operation period than built-in potentials of the pn junctions between the respective sources and substrates. Therefore, no forward current (leak current) occurs on the pn junctions when the substrate voltages of the PMOS transistor and the nMOS transistor are set at a value between the first power supply voltage and the second power supply voltage. The absence of leak currents precludes fluctuations in substrate voltage. Accordingly, the threshold voltages of the transistors are maintained at a predetermined value, with no variations in the drivabilities of the transistors. In addition, a current increase caused by turning-on of the pn junctions, latch-up, and the like are prevented from occurring.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate voltage of the pMOS transistor and the substrate voltage of the nMOS transistor are set at a value at the center of the first power supply voltage and the second power supply voltage during the operation period of the transistors. Therefore, differences (margins) between the source-to-substrate voltages of the transistors and the built-in potentials can be equally large. It is also possible to equalize variations in the threshold voltages of the transistors during the operation period.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate voltage of the pMOS transistor and the substrate voltage of the nMOS transistor are set equal to each other during the operation period of the transistors. Thus, the substrate voltages are set at a value between the first power supply voltage and the second power supply voltage by, for example, connecting the substrate of the PMOS transistor and the substrate of the nMOS transistor to each other.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate voltage of the pMOS transistor and the substrate voltage of the nMOS transistor are respectively set at the first power supply voltage and the second power supply voltage during the non-operation period of the transistors. The threshold voltages of the transistors are higher than during the operation period. This reduces leak currents in the transistors during the non-operation period.
According to another aspect of the semiconductor integrated circuit in the present invention, a voltage higher than the first power supply voltage is temporarily supplied to a substrate of the pMOS transistor when the substrate voltage of the pMOS transistor is generally set at the first power supply voltage. Therefore, when the pMOS transistor shifts from an operation state to a non-operation state, its substrate voltage swiftly turns to the first power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit includes a capacitor charged by applying a voltage higher than the first power supply voltage. When the substrate voltage of the pMOS transistor is set at the first power supply voltage, the substrate of the pMOS transistor is connected to the capacitor. As a result, the substrate voltage of the pMOS transistor turns to the first power supply voltage through the use of the charge stored in the capacitor. That is, the capacitor assists in setting the substrate voltage at the first power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, a voltage lower than the second power supply voltage is temporarily supplied to the substrate of the nMOS transistor when the substrate voltage of the nMOS transistor is generally set at the second power supply voltage. Therefore, when the nMOS transistor shifts from an operation state to a non-operation state, its substrate voltage swiftly turns to the second power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit includes a capacitor charged by applying a voltage lower than the second power supply voltage. When the substrate voltage of the nMOS transistor is set at the second power supply voltage, the substrate of the nMOS transistor is connected to the capacitor. As a result, the substrate voltage of the nMOS transistor turns to the second power supply voltage through the use of the charge stored in the capacitor. That is, the capacitor assists in setting the substrate voltage at the second power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate of the pMOS transistor and the substrate of the nMOS transistor are connected to each other during the operation period of the pMOS transistor and the nMOS transistor. The substrate voltages can be easily set at a value between the first power supply voltage and the second power supply voltage by short-circuiting the substrates of the pMOS transistor and the nMOS transistor to each other.
According to another aspect of the semiconductor integrated circuit in the present invention, the substrate of the pMOS transistor and the substrate of the nMOS transistor, which are charged by applying different voltages, are connected to each other during the operation period of the pMOS transistor and the nMOS transistor. The charges stored in the substrates are shared in accordance with a junction capacitance ratio between the substrates, whereby the substrate voltages easily become equal to each other. Besides, the substrate voltages can be set at a desired value in accordance with a junction capacitance ratio between the pMOS transistor and the nMOS transistor.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit includes a capacitor charged by applying a predetermined voltage. During the operation period of the transistors, the substrates of the transistors are connected to the charged capacitor, thereby obtaining a predetermined voltage. Therefore, the substrate voltages can be set at a desired value in accordance with the junction capacitance and the junction capacitance ratios of the transistor substrates.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit includes an nMOS transistor. A substrate of the nMOS transistor is supplied with an external power supply voltage until the power supply voltage reaches a predetermined value, the external power supply voltage being supplied from exterior. Alternatively, a substrate of the nMOS transistor is supplied with an internal power supply voltage until the internal power supply voltage reaches a predetermined voltage, the internal power supply voltage being generated from the external power supply voltage. This lowers the threshold voltage of the nMOS transistor upon the startup of the power supply. For example, when the semiconductor integrated circuit has a power-on resetting circuit, which utilizes the threshold voltage of the nMOS transistor to generate a power-on resetting signal, then it is possible to advance the transition edge (inactivation timing) of the power-on resetting signal. On this account, the power-on resetting signal can be generated with reliability, particularly when the threshold voltage of the nMOS transistor is relatively high with respect to the power supply voltage or the internal power supply voltage.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit includes a pMOS transistor. A substrate of the pMOS transistor is supplied with a ground voltage until an external power supply voltage reaches a predetermined value. Alternatively, a substrate of the pMOS transistor is supplied with a ground voltage until an internal power supply voltage generated from the external power supply voltage reaches a predetermined voltage. This lowers the threshold voltage of the pMOS transistor upon the startup of the power supply. For example, when the semiconductor integrated circuit has a power-on resetting circuit, which utilizes the threshold voltage of the pMOS transistor to generate a power-on resetting signal, then it is possible to advance the transition edge (inactivation timing) of the power-on resetting signal. On this account, the power-on resetting signal can be generated with reliability, particularly when the threshold voltage (in absolute value) of the pMOS transistor is relatively high with respect to the power supply voltage or the internal power supply voltage.